1. Field of the Invention
The present invention relates to the direct processing of delta sigma modulated (DSM) and linear delta modulated (LDM) pulse streams. The sensing signal (analog input signal) is first converted into a one-bit high density (oversampled) pulse stream using DSM or LDM oversampled analog-to-digital converter. To implement a particular linear or nonlinear function, dedicated circuits have to be developed. Thus, the field of this invention is a pulse signal processing of one-bit non-positional delta modulated stream. It belongs to a wider class of digital signal processing (DSP) in the electrical engineering field.
2. Description of the Prior Art
The conventional method of DSP of a DSM pulse stream is achieved by using a decimation technique to interface with existing n-bit DSP hardware. Existing n-bit DSP hardware is bulky, power consuming, and prone to errors. Typical DSP hardware consists of a micro-processor and supporting n-bit communication lines with centralized control and synchronization. This hardware is not suitable for sub-micron technology because n-bit processors are hierarchical systems (every bit is weighted), and when the most significant bit (MSB), or sign bit is in error, a catastrophic malfunction can happen. To take advantage of the non-positional nature of a DSM pulse stream, there were several attempts to develop circuits for linear processing of a DSM pulse stream [U.S. Pat. No. 6,587,061 B2; U.S. Pat. No. 7,609,187 B2].
The earliest publications on the use of DSM in signal processing comes from Lockhart [1]. Digital filter coefficients are made of resistive networks. A similar idea is used by Lockhart and Babary [2] to implement an infinite impulse response (IIR) filter using a recalculating shift register. In both publications resistors are used to add filter coefficients.
Publications of Peled and Liu [3], [4] use ordinary DSP hardware to implement delta-modulated based digital filters. The implementation of filter coefficients is achieved using read-only memory (ROM).
In 1978 Lagoyannis [5] proposed a new method for multiplying delta-modulated signals by a constant. He implemented a digital circuit for direct multiplication of a delta modulated sequence.
In 1978, Locicero et al. [6] proposed a method for direct processing of adaptive delta-modulated (ADM) signals. By operating on the serial DM bit streams, sum, difference and product can be obtained in PCM and DM format. An arithmetic processor uses ordinary DSP hardware.
In the period 1978-1985, Kouvaras published a number of papers related to linear processing of a delta modulated stream. In reference [7] Kouvaras proposed a new method with which is possible to find a delta-modulated signal of the half sum of two analog signals through direct operation of their delta-modulated form. He proposed hardware implementation of a delta adder and did error analysis of the proposed circuit. In reference [8] Kouvaras proposes a digital circuit for doubling the amplitude of a delta modulated signal. In fact, by using a delta doubler, it is possible to overcome the problem of attenuation of one-half which the delta adder introduces [7]. In reference [9] Kouvaras proposed several circuits for the direct multiplication of delta-modulated signals by constants. In addition to a non-recursive form, Kouvaras proposed a recursive form of the multiplier. In reference [10] Kouvaras proposed a new modular multi-input network for direct arithmetic operation on DM signals. In reference [11] Kouvaras proposed a technique for the reduction of the quantization noise in the direct processing of a DM pulse stream. In reference [12] Kouvaras proposed the modular network for the direct addition of DM signals with minimum quantization noise.
Lagoyannis and Pekmestzi proposed multipliers of two DM sequences [13]. These multipliers provide the product in DM sequence form. These multipliers were used in the implementation of a parallel type of digital correlator.
In reference [14] Zrilic et al. proposed the implementation of a ternary delta adder and ternary delta multiplier for the implementation of digital filters. In reference [15] Freedman and Zrilic proposed a new algorithm for linear and non-linear processing of a DM pulse stream. In reference [16] Zrilic proposed a number of circuits for linear, nonlinear and direct processing of a DM pulse stream. In his patents (U.S. Pat. No. 5,349,353 and U.S. Pat. No. 6,285,306 B1), Zrilic disclosed the number of circuits for linear, nonlinear and mixed processing of a DSM pulse stream.
In reference [17] Wong and Gray present two methods for building FIR filters based on single-loop and two-stage DSM encoding. These filters do not require multipliers.
Horianoupulos et al. [18] proposed a design technique for hardware reduction in delta modulated FIR filters. This method takes advantage of the special characteristics of DM filters in order to reduce noise.
Johns and Lewis [19] designed and analyzed delta-sigma filters by eliminating all multi-bit multipliers through the use of re-modulating internal filter states.